Program for 2015 28th IEEE International System-on-Chip Conference (SOCC)
Tuesday, September 8
08:30 - 10:00
T1A: Tutorial: Phase-Locked Clock Generation for SoC: Circuit and System Design Aspects
Woogeun Rhee, Tsinghua University, China
Room: Da Xue Tang-2Chair: Helen Li (University of Pittsburgh, USA)
T1B: Tutorial: SoC Testing
Yu Huang and Janusz Rajski, Mentor Graphics, USA
Room: Da Xue Tang-4Chair: Yuejian Wu (Infinera, Canada)
10:00 - 10:30
Tea Break
10:30 - 12:00
T2A: Tutorial: Advanced ESD Protection Design for CMOS Circuits and Systems
Ming-Dou Ker, NCTU, Taiwan
Room: Da Xue Tang-2Chair: Helen Li (University of Pittsburgh, USA)
T2B: Tutorial: Internet of Things (IoT) - Opportunities for SoC Designers
Ramalingam Sridhar, University Buffalo, USA
Room: Da Xue Tang-4Chair: Yuejian Wu (Infinera, Canada)
12:00 - 13:30
Lunch Break
13:30 - 15:00
T3A: Tutorial: From Frequency to Time-Average-Frequency: A paradigm Shift in the Design of Electronic Systems
Liming Xiu, Kairos Microsystems Corp.
Room: Da Xue Tang-2Chair: Helen Li (University of Pittsburgh, USA)
T3B: Tutorial: A Self-powered Biomedical SoC for Wearable Health Care
Mohammed Ismail, KUSTAR, Abu Dhabi, UAE
Room: Da Xue Tang-4Chair: Yuejian Wu (Infinera, Canada)
15:00 - 15:30
Tea Break
15:30 - 17:00
T4A: Tutorial: Tiny DC-Sourced Single Inductor Charge-Supply ICs
Gabriel Rincón-Mora, Georgia Inst. of Tech, USA
Room: Da Xue Tang-2Chair: Helen Li (University of Pittsburgh, USA)
T4B: Tutorial: Emerging Non-volatile Memory: Device, Circuit, and Architecture
Guangyu Sun, Peking University
Room: Da Xue Tang-4Chair: Yuejian Wu (Infinera, Canada)
Wednesday, September 9
08:00 - 08:15
Opening Remarks
Thomas Buechner, Shao-Jun Wei, Conference General Chairs
Room: Zhong Hua Banquet HallChair: Thomas Buechner (IBM Germany Research & Development, Germany)
08:15 - 08:30
Program Overview
Danella Zhao, Program Chair
Room: Zhong Hua Banquet HallChair: Danella Zhao (University of Louisiana at Lafayette, USA)
08:30 - 09:30
Opening Keynote
Jason Cong, Chancellor's Professor, UCLA and Director, Center for Domain-Specific Computing
Room: Zhong Hua Banquet HallChair: Thomas Buechner (IBM Germany Research & Development, Germany)
09:30 - 09:45
Tea Break
09:45 - 10:45
Plenary I
"Venice: A Cost-effective Architecture for Datacenter Servers"
Rui Hou, VP Processor Design, Suzhou PowerCore
Room: Zhong Hua Banquet HallChair: Thomas Buechner (IBM Germany Research & Development, Germany)
10:50 - 12:05
WA1A: Best Paper Nomination I
Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
- WA1A.1 10:50 A 12-bit 1.7mW 20-MS/s DAC with Resistor-String and Current-Steering Hybrid Architecture
- WA1A.2 11:15 A Process-Variation-Aware Multi-Scenario High-Level Synthesis Algorithm for Distributed-Register Architectures
- WA1A.3 11:40 Designing a SoC to Control Next-Generation Space Exploration Science Instruments
WA1B: RF, Analog & Mixed-Signal I
Room: Da Xue Tang-2
Chairs: Mohammed Ismail (Khalifa University, UAE), Peng Liu (Zhejiang University, P.R. China)
- WA1B.1 10:50 A 20 GHz High Speed, Low Jitter, High Accuracy and Wide Correction Range Duty Cycle Corrector
- WA1B.2 11:15 A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS
- WA1B.3 11:40 All-Digital Deskew Buffer Using a Hybrid Control Scheme
12:05 - 13:30
Lunch Break
13:30 - 15:10
WP1A: SOC Outreach Workshop Keynotes
Juergen
Becker, Karlsruhe Institute of Technology, Germany; Magdy Bayoumi,
University of Louisiana at Lafayette, USA; Michiko Inoue, Nara Institute
of Science and Technology, Japan
Room: Zhong Hua Banquet HallChair: Danella Zhao (University of Louisiana at Lafayette, USA)
WP1B: Wireline & Wireless Communications
Room: Da Xue Tang-2
Chairs: Zhongfeng Wang (Broadcom Corp., USA), Gabriel Rincón-Mora (Georgia Institute of Technology, USA)
- WP1B.1 13:30 A 0.68 pJ/bit Inductor-less Optical Receiver for 20 Gbps with 0.0025mm2 Area in 28 nm CMOS
- WP1B.2 13:55 A 320MHz-2.56GHz Low Jitter Phase-Locked Loop with Adaptive-Bandwidth Technique
- WP1B.3 14:20 A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
- WP1B.4 14:45 A 1.2V Wide-Band Reconfigurable Mixer for Wireless Application in 65nm CMOS Technology
WP1C: System Level Design Methodologies
Room: Da Xue Tang-4
Chairs: Yu Wang (Tsinghua University, P.R. China), Suhwan Kim (Seoul National University, Korea)
- WP1C.1 13:30 Statistical Rare Event Analysis Using Smart Sampling and Parameter Guidance
- WP1C.2 13:55 Per-Flow State Management Technique for High-Speed Networks
- WP1C.3 14:20 KnapSim- Run-time Efficient Hardware-Software Partitioning Technique for FPGAs
- WP1C.4 14:45 Optimal Realization of Switched-Capacitor Circuits by Symbolic Analysis
15:10 - 15:30
Tea Break
15:30 - 16:30
WP2A: SOC Outreach Workshop Panel
Technology, Leadership, Women - Challenges & Opportunities
Michiko Inoue, Nara Institute of Science and
Technology, Japan; Yi-Jung Chen, National Chi Nan University, Taiwan;
Summer Xinhong Yin, Broadcom Beijing; Junna Zhong, Menter Graphics
Shanghai
Room: Da Xue Tang-2Chair: Ann Gordon-Ross (University of Florida, USA)
15:30 - 16:45
WP2B: Design track
Room: Da Xue Tang-4
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)
- WP2B.1 15:30 SCREAMER - A Demonstrator Chip for Spectral Noise Optimization by Clock Latency Scheduling
- WP2B.2 15:45 14nm FinFET Mobile Application Processor with Heterogeneous Multi-Processing Quad-Core CPUs
- WP2B.3 16:00 Scan-Hold-Timing-Friendly Flip-Flop to Improve Chip Routing and Power
- WP2B.4 16:15 A Robust Architecture for a Complex On-Chip Power Management Controller with External Regulator Handshake for Automotive SOCs
- WP2B.5 16:30 Low-latency Packet Classification Architectures for an FPGA-based IPv6 Processor
16:50 - 18:00
WP: Poster Session with Reception
Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
- WP.1 A Tunable Inverter-Based, Low-Voltage OTA for Continuous-Time ΣΔ ADC
- WP.2 A High-Gain Low-Power Low-Noise-Figure Differential CMOS LNA with 33% Current-Reused Negative-Conductance Accommodation Structure
- WP.3 A Comparative Study of multi-GHz LCVCOs Designed in 28nm CMOS Technology
- WP.4 Multi-Objective Optimization of a Low-Noise Antenna Amplifier for Multi-Constellation Satellite-Navigation Receivers
- WP.5 A Digital-Control Sensorless Current-Mode Boost Converter with Non-Zero Error Bin Compensation and Seamless Mode Transition
- WP.6 Novel ECC Structure and Evaluation Method for NAND Flash Memory
- WP.7 Floorplan and Congestion Aware Framework for Optimal SRAM Selection for Memory Subsystems
- WP.8 An Improved Distributed Video Coding with Low-Complexity Motion Estimation At Encoder
- WP.9 Modelling Visual Attention Towards Embodiment Cognition on a Reconfigurable and Programmable System
- WP.10 A Filter Design to Increase Accuracy of Lucy- Richardson Deconvolution for Analyzing RTN Mixtures Effects on VLSI Reliability Margin
- WP.11 Analysis of a Serial Link for Power Supply Induced Jitter
- WP.12 Formal Equivalence Checking Between SLM and RTL Descriptions
- WP.13 An Accelerator for Classification Using Radial Basis Function Neural Network
- WP.14 Reconfigurable Hardware Architecture of the Spatial Pooler for Hierarchical Temporal Memory
- WP.15 Low-Voltage 9T FinFET SRAM Cell for Low-Power Applications
- WP.16 Low Power Design for On-chip Networking Processing System
- WP.17 A High Throughput Router with a Novel Switch Allocator for Network on Chip
- WP.18 Fault-Resilient Routing Unit in NoCs
- WP.19 A 9-bit, 110-MS/s Pipelined-SAR ADC Using Time-Interleaved Technique with Shared Comparator
- WP.20 Design of A 12-bit 0.83 MS/s SAR ADC for an IPMI SoC
- WP.21 Instruction Decoders Based on Pattern Factorization
- WP.22 A Multi-level Collaboration Low-power Design Based on Embedded System
- WP.23 A Deterministic, Minimal Routing Algorithm for a Toroidal, Rectangular Honeycomb Topology Using a 2-tupled Relative Address
- WP.24 An A-SAR ADC Circuit with Adaptive Auxiliary Comparison Scheme
19:30 - 20:40
Legend Of Kung Fu Show at Red Theatre (included in full conference registration, transportation provided)
Thursday, September 10
08:30 - 09:30
Thursday Keynote
Five Forces Shaping the Silicon World: Advanced sensing and intelligence in IoT and vision
Chris Rowen, Fellow and CTO IP Group Cadence Design Systems, Inc.
Room: Zhong Hua Banquet HallChair: Thomas Buechner (IBM Germany Research & Development, Germany)
09:30 - 10:30
Plenary II
Unicorns and Centaurs: Architecting SOCs for Software Defined Networking
Gavin Stark, Chief Scientist, Netronome
Room: Zhong Hua Banquet HallChair: Thomas Buechner (IBM Germany Research & Development, Germany)
10:30 - 10:45
Tea Break
10:45 - 12:00
TA1: Best Paper Nomination II
Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
- TA1.1 10:45 Can Systems Extend to Polymer? SoP Architecture Design and Challenges
- TA1.2 11:10 FAcET: Fast and Accurate Power/Energy Estimation Tool for CPU-GPU Platforms At Architectural-Level
- TA1.3 11:35 Symmetric Write Operation for 1T-1MTJ STT-RAM Cells Using Negative Bitline Technique
TA1B: RF, Analog & Mixed-Signal II
Room: Da Xue Tang-2
Chairs: Guoyong Shi (Shanghai Jiao Tong University, P.R. China), Andrew Marshall (University of Texas at Dallas, USA)
- TA1B.1 10:45 A PAM-4 Adaptive Analog Equalizer with Decoupling Control Loops for 25-Gb/s CMOS Serial-Link Receiver
- TA1B.2 11:10 Low Noise Output Stage for Oversampling Audio DAC
- TA1B.3 11:35 A Digital Background Calibration Technique for Split DAC Based SAR ADC by Using Redundant Cycle
12:00 - 13:30
Lunch Break
13:30 - 15:10
TP1A: Embedded Computing Systems & Applications
Room: Da Xue Tang-2
Chairs:
Sao-Jie Chen (National Taiwan University, Taiwan), Sakir Sezer (Queen's
University Belfast & CTO Titan IC, United Kingdom)
- TP1A.1 13:30 A 61 μA/MHz Reconfigurable Application-Specific Processor and System-on-Chip for Internet-of-Things
- TP1A.2 13:55 A Point of Care Electrochemical Impedance Spectroscopy Device
- TP1A.3 14:20 Energy-Efficient Gas Recognition System with Event-Driven Power Control
- TP1A.4 14:45 Loop Acceleration and Instruction Repeat Support for Application Specific Instruction-set Processors
TP1B: High-Level Synthesis & Verification
Room: Da Xue Tang-3
Chairs: Yu Huang (Mentor Graphics, USA), Michiko Inoue (Nara Institute of Science and Technology, USA)
- TP1B.1 13:30 Synthesis and Verification of Cyclic Combinational Circuits
- TP1B.2 13:55 Partitioning-Based Multiplexer Network Synthesis for Field-Data Extractors
- TP1B.3 14:20 A Scan Segmentation Architecture for Power Controllability and Reduction
- TP1B.4 14:45 Optimization of Best Polarity Searching for Mixed Polarity Reed-Muller Logic Circuit
TP1C: NoC & Multicore Architecture
Room: Da Xue Tang-4
Chairs:
Ann Gordon-Ross (University of Florida, USA), Yinhe Han (Institute of
Computing Technology, Chinese Academy of Sciences, P.R. China)
- TP1C.1 13:30 A Novel Flow Fluidity Meter for BiNoC Bandwidth Resource Allocation
- TP1C.2 13:55 Low-Latency Power-Efficient Adaptive Router Design for Network-on-Chip
- TP1C.3 14:20 A Novel Fault-Tolerant Router Architecture for Network-on-Chip Reconfiguration
- TP1C.4 14:45 Adaptive CDMA Based Multicast Method for Photonic Networks on Chip
15:10 - 15:30
Tea Break
15:30 - 17:00
Panel Discussion
How to Avoid Internet of "Broken" Things - Challenges in Integration, Reliability, Security and Scalability
Shin-Ming Liu, Chief Scientist, Intel Labs
China; Gavin Stark, Chief Scientist, Netronome; Yervant Zorian, Chief
Architect and Fellow, Synopsys; Lan Chen, Professor & Deputy
Director of China R&D Center for Internet of Things, CAS; Zhong
Chen, Professor of EECS, Peking University; YongPan Liu, Associate
Professor of EE, Tsinghua University
Room: Zhong Hua Banquet HallChair: Magdy Bayoumi (University of Louisiana, USA)
19:00 - 21:30
Banquet Dinner & Keynote (Beijing Fangshan Restaurant - transportation provided)
Yervant Zorian, Chief Architect and Fellow, Synopsys
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)
Friday, September 11
08:30 - 10:10
FA1A: Memory Systems
Room: Da Xue Tang-2
Chairs: Juergen Becker (Karlsruhe Institute of Technology, Germany), Guangyu Sun (Peking University, P.R. China)
- FA1A.1 08:30 A 128-kb 10% Power Reduced 1T High Density ROM with 0.56ns Access Time Using Bitline Edge Sensing in Sub 16 nm Bulk FinFET Technology
- FA1A.2 08:55 A 6T SRAM Cell Based Pipelined 2R/1W Memory Design Using 28nm UTBB-FDSOI
- FA1A.3 09:20 Statistical Analysis and Parametric Yield Estimation of Standard 6T SRAM Cell for Different Capacities
- FA1A.4 09:45 Memory Cost Analysis for OpenFlow Multiple Table Lookup
FA1B: Low Power Systems & Design Methodologies
Room: Da Xue Tang-3
Chairs: Shiyan Hu (Michigan Technological University, USA), Yuejian Wu (Infinera, Canada)
- FA1B.1 08:30 A -30 Dbm Sensitive Ultra Low Power RF Energy Harvesting Front End with an Efficiency of 70.1% At -22 Dbm
- FA1B.2 08:55 VCAS: Viewing Context Aware Power-Efficient Mobile Video Embedded Memory
- FA1B.3 09:20 Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
- FA1B.4 09:45 A High Speed and Low Power Content-addressable Memory(CAM) Using Pipelined Scheme
08:30 - 09:45
FA1C: Design and CAD Research Opportunities in Post-CMOS Era
Special Session I
Room: Da Xue Tang-4Chairs: Yiyu Shi (Missouri Univ of Science & Technology, USA), Guojie Luo (Peking University, P.R. China)
- 08:30 The Evolutionary Spintronic Technologies and Their Usage in High Performance Computing
- 08:55 On Microarchitectural Modeling for CNFET-based Circuits
- 09:20 Timing-Driven Placement for Carbon Nanotube Circuits
10:10 - 10:30
Tea Break
10:30 - 12:10
FA2A: Multi-domain Power Management
Room: Da Xue Tang-2
Chairs: Mohammed Ismail (Khalifa University, UAE), Ramalingam Sridhar (University at Buffalo, USA)
- FA2A.1 10:30 Cascoded Flipped Voltage Follower Based Output-Capacitorless Low-Dropout Regulator for SoCs
- FA2A.2 10:55 A Fully Integrated Charge Sharing Active Decap Scheme for Power Supply Noise Suppression
- FA2A.3 11:20 ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
- FA2A.4 11:45 High-PSR CMOS LDO with Embedded Ripple Feed-Forward and Energy-Efficient Bandwidth Extension
FA2B: On-Chip Interconnect & 3D-IC
Room: Da Xue Tang-3
Chairs:
Sao-Jie Chen (National Taiwan University, Taiwan), Sakir Sezer (Queen's
University Belfast & CTO Titan IC, United Kingdom)
- FA2B.1 10:30 Exploiting Multi-Band Transmission Line Interconnects to Improve the Efficiency of Cache Coherence in Multiprocessor System-on-Chip
- FA2B.2 10:55 Research on Crosstalk Issue of Through Silicon Via for 3D Integration
- FA2B.3 11:20 Analysis and Design of High Performance Wireless Power Delivery Using On-chip Octagonal Inductor in 65-nm CMOS
- FA2B.4 11:45 A Novel Thermal-Aware Structure of TSV Cluster
FA2C: Emerging VLSI DSP Techniques for Next Generation Communication
Special Session II
Room: Da Xue Tang-4Chairs:
Chuan Zhang (National Mobile Communications Research Laboratory,
Southeast University, P.R. China), Liping Li (Anhui University, P.R.
China)
- 10:30 High-throughput MQ Encoder for Pass-Parallel EBCOT in JPEG2000
- 10:55 On the Encoding Complexity of Systematic Polar Codes
- 11:20 Efficient Stochastic List Successive Cancellation Decoder for Polar Codes
- 11:45 EM Independent Gaussian Approximate Message Passing and Its Application in OFDM Impulsive Noise Mitigation
13:30 - 18:00
Beijing Tour: Tiananmen square, forbidden city, Hutong tour (with rickshaw) - Not included in conference fees
13:30 - 14:30
Tech tour of Spreadtrum Communications, Inc.
Welcome & Introduction
Yi Kang, VP of Spreadtrum