September 8-11, 2015
The Lakeview Hotel
Beijing, China

Wednesday Keynote Speaker

Jason Cong
Chancellor's Professor, UCLA Computer Science Department
Director, Center for Domain-Specific Computing

University of California, Los Angeles

High-Level Synthesis and Beyond – from Datacenters to IoTs

Jason Cong

Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the UCLA Computer Science Department, the director of Center for Domain-Specific Computing (CDSC). He served as the department chair from 2005 to 2008. Dr. Cong's research interests include electronic design automation, energy-efficient computing, customized computing for big-data applications, and highly scalable algorithms. He has over 400 publications in these areas, including 10 best paper awards, and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System Society Technical Achievement Award "For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation."

Dr. Cong has graduated 33 PhD students. Nine of them are now faculty members in major research universities, including Cornell, Fudan Univ., Georgia Tech., Peking Univ., Purdue, SUNY Binghamton, UCLA, UIUC, and UT Austin. Dr. Cong has successfully co-founded three companies with his students, including Aplus Design Technologies for FPGA physical synthesis and architecture evaluation (acquired by Magma in 2003, now part of Synopsys), AutoESL Design Technologies for high-level synthesis (acquired by Xilinx in 2011), and Neptune Design Automation for ultra-fast FPGA physical design (acquired by Xilinx in 2013). Currently, he is a co-founder of Falcon Computing Solutions, a startup dedicated to enabling FPGA-based customized computing in data centers. Dr. Cong is also a distinguished visiting professor at Peking University (PKU), a co-director of UCLA/PKU Joint Research Institute in Science and Engineering, and the director for PKU Center for Energy-Efficient Computing and Applications (CECA).

Abstract: In SOCC'2006, my group presented an invited paper on xPilot – the high-level synthesis (HLS) tool developed at UCLA for automatic synthesis of behavior-level C/C++ specifications into highly optimized RTL code. In the same year, The startup company AutoESL was formed to commercialize our research on HLS – an effort that many EDA companies tried but failed for over two decades. Nevertheless, the AutoESL tool (renamed to Vivado HLS after Xilinx acquisition in 2011) becomes probably the most successful and most widely used HLS tool in the history, with over tens of thousands of users from over 3,000 companies and universities worldwide (as of Feb. 2015). In this talk, I shall first share the lessons that we learned from our HLS project. Then, I shall discuss the new opportunities enabled by a robust HLS technology, from data centers to IoTs. At one end, the HLS technology can be an important building block to enable customized computing in data centers, leading to significant improvement of performance-energy efficiency. At the other extreme, HLS can enable rapid design of highly customized IoT nodes for vastly different applications, enabling best possible optimization in cost and energy efficiency. To embrace such opportunities, our recent research focuses on (i) source-code level transformation and optimization for efficient accelerator designs, such as polyhedral-based data reuse optimization and code generation, uniform and non-uniform memory partitioning, and simultaneous computation and communication optimization; (ii) datacenter-level runtime management for transparent and efficientaccelerator utilization; and (iii) cost-efficient synthesis of complex SoCs that integrates heterogeneous components, including digital and analog processing units and various sensing and communication devices. I shall highlight some key progresses in these directions. 

Wednesday Plenary Speaker

Rui Hou
Vice President Processor Design
Suzhou PowerCore
, and
Associate Professor
Institute of Computing Technology, Chinese Academy of Sciences.

Venice: A Cost-effective Architecture for Datacenter Servers”

RuiHouRui Hou is VP, Processor Design, of Suzhou PowerCore Technology. He received his Bachelor’s and Master’s degree in computer science from Harbin Institute of Technology in 1999 and 2003 respectively, and earned his Ph.D in computer science from the Institute of Computing Technology of the Chinese Academy of Sciences in 2007. His main research interests are in the areas of data center systems and high-performance CPUs. Dr. Hou is currently leading a team to develop a high performance server processor based on IBM’s Power technology. He has led the design and development of an ARMv8 based many-core processor with a brand-new SMT-4 core that his team designed from the scratch. He has built prototypes systems enabling efficient resource sharing and high throughput computing inside the data centers. Dr. Hou is also an associate professor at Institute of Computing Technology. Before joining ICT in 2011, he had been working at IBM China Research Lab for four years. He has published over 20 peer-reviewed papers in various international conferences and journals, and filed more than 50 patent applications.

Abstract: Consolidated datacenter server racks are quickly becoming the backbone of IT infrastructure for science, engineering, and business alike. To a large extent, these datacenter servers are still built and organized as when they were distributed, individual entities. Given that many fields increasingly rely upon analytics of huge datasets, it makes sense to more tightly join servers to better share critical but expensive resources. In this talk, I will introduce Venice, a cost-effective datacenter server architecture that breaks though the hardware boundaries of traditional physical nodes and provides a set of resource-joining mechanisms that enables nodes can easily and efficiently use remote idle resources according to the dynamic workload requirements. A series of hardware prototyping systems were implemented to evaluate the design of Venice architecture.

Thursday Keynote Speaker

Chris Rowen
Fellow and CTO, Design Group
Cadence Design Systems, Inc.

Five Forces Shaping the Silicon World: Advanced sensing and intelligence in IoT and vision”

RowenChris Rowen is the Chief Technology Officer for Cadence's IP Group. He is developing extensible processor IP that can be configured easily into custom chips for applications in wireless, peripheral control, imaging, and other areas. He joined Cadence after its acquisition of Tensilica, the company he founded to develop extensible processors. He built Tensilica to the point where its processors had more than 200 licensees, including seven of the top 10 chip companies, who had shipped more than 2 billion cores. Before founding Tensilica, he was VP and General Manager of the Design Reuse Group at Synopsys. He also was a pioneer in developing RISC architecture and helped start MIPS Computer Systems, where he was Vice President for Microprocessor Development. He holds an MSEE and PhD in electrical engineering from Stanford (working under John Hennessy) and a BA in physics from Harvard.

Abstract: The cumulative improvement in digital silicon density, energy and performance has had an impressive quantitative impact on the world we live in. But new forces, embodied in radical changes in system applications, are rapidly disrupting traditional silicon architectures. In this talk we chart five of the major forces at work in silicon systems, and explore new categories of "things that sense and see". Along the way, we visit some fundamental shifts taking place in low-energy processor cores, in vision DSPs, and in systems for "deep learning" that now exceed human capabilities.

Thursday Plenary Speaker

Gavin Stark
Chief Scientist, Netronome

Unicorns and Centaurs: Architecting SOCs for Software Defined Networking

stark-bio-photoGavin Stark has been designing high speed communications systems for over 20 years.  At Netronome he is now developing his seventh generation of network processing architecture. Prior to Netronome, Gavin held chief architect and CTO positions at Virata, Cirrus Logic and Basis Communications, which was acquired by Intel Corporation.  Gavin holds both an MA and a PhD from Cambridge University, England. Gavin holds several patents in areas including packet processing algorithms and network processor architecture.

Abstract: Software Defined Networks (SDN) are a major development in communications, providing a means for controlling and reducing the complexity of managing the many protocols and layers that are in modern networks, and aiding virtualization of networks using a myriad of tunneling techniques. As with most complex systems there are (at least) two perspectives on SDN: a view from the hardware, where SDN is about feeding the silicon systems that are driven by the slow evolution of network silicon progress; and a view from above, a software perspective, where the requirements come from replicating and enhancing the features used in legacy equipment. The reconciliation of these two viewpoints is difficult at a network appliance level, and even harder at an SOC level. We will explore these two perspectives and this reconciliation in various SOC architectures, and investigate how these various architectures satisfy the needs of the networks.

Banquet Keynote Speaker

Yervant Zorian
Chief Architect and Fellow, Synopsys

Ensuring Robustness in Today’s SOCs

yervant-zorianYervant Zorian is a Chief Architect and Fellow at Synopsys. Formerly, he was a Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic, and Chief Technologist at LogicVision. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 34 US patents, has authored 4 books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Abstract: Today’s SOC design teams, from mobile applications to Internet of Things (IoT), use a mix of challenging technologies, use multi-level hierarchical architectures to handle design size explosion and liberal use of 3rd-party blocks (IPs, cores, and sub-systems). To ensure robustness in these SOC, it has become crucial to use advanced yield and reliability solutions. This presentation will discuss key trends and challenges in today’s SOCs, and will cover a range of solutions from design for debug, reliability and test, to post-silicon analysis and yield optimization trade-offs using volume diagnosis, reconfiguration and self-repair.

 SoC Outreach Keynotes

Jürgen Becker
Karlsruhe Institute of Technology - KIT, Germany

"Hardware/Software System-on-Chip Solutions for Heterogenous Safety-Critical Multi-Core Technologies"


Juergen Becker received the Diploma degree in 1992, and his Ph.D. (Dr.-Ing.) degree in 1997, both at Kaiserslautern University, Germany. His research work focused on application development environments for reconfigurable accelerators and included hardware/software codesign, parallelizing compilers, customized computing, and high-level synthesis. He has been local administrator for the European Design Project EUROCHIP in 1993/95. In 1997 Dr. Becker joined the Institute of Microelectronic Systems at Darmstadt University of Technology, Germany, as assistant professor, where he taught CAD algorithms for VLSI design. He did research in Systems-on-Chip (SoC) architectures and reconfigurable technologies for mobile communication systems, including the development of corresponding IP-based CAD methods.

Since 2001 Juergen Becker is professor for embedded electronic systems at the Institut fuer Technik der Informationsverarbeitung (ITIV) at the University of Karlsruhe. He gives lectures in digital design (undergraduate), in CAD algorithms for high-level synthesis and VLSI design, hardware/software codesign, as well as in bus interfaces and protocols. His actual research is focused on industrial-driven SoCs with emphasis on adaptive embedded systems, e.g. dynamically reconfigurable hardware architectures. This includes corresponding hardware/software codesign and co-synthesis techniques from high-level specifications, as well as low power SoC optimization. Prof. Becker is co-director of the Embedded Systems and Sensors Engineering (ESS) group at the Computer Science Research Center (FZI) .

He is author and co-author of more than 400 scientific papers (+ more than 10 patents), published in peer-reviewed international journals and conferences and active in several technical program and steering committees of international conferences and workshops. He is a Member of the german GI and Senior Member of the IEEE. Prof. Becker is chair of the GI/ITG Technical Committee of 'Architekturen fuer hochintegrierte Schaltungen' and is member of "Editorial Board of IEEE Transaction on Computers" and "Executive Committee der Deutschen Sektion des IEEE" . Prof. Becker started in October 2004 as VicePresident of Universität Karlsruhe (TH) responsible for the area Studies and Teaching, respectively since October 2009 to March 2012 as Chief Higher Education Officer (CHEO) of the KIT.

Since 2012 on he serves as Secretary General of CLUSTER , an association of 12 leading technical universities in Europe. In 2013 Prof. Becker received the Honorary Doctor award (Dr. h. c.) from Technical University Budapest (Hungary).

Abstract: The field of embedded electronic systems, nowadays also called cyper-physical systems, is still emerging. A cyber-physical system (CPS) is a system featuring a tight combination of, and coordination between, the system's computational and physical elements. Today, a pre-cursor generation of cyber-physical systems can be found in areas as diverse as space, avionics, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing, transportation, entertainment, and consumer appliances. This generation is often referred to as embedded systems. In embedded systems the emphasis tends to be more on the computational elements, and less on an intense link between the computational and physical elements.

Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy, computing and cost constraints. My view is of an "all-win-symbiosis" of future silicon-based processor technologies and reconfigurable circuits/architectures. Moreover, dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing in addition high adaptivity for a range of applications and situations. Reliability, failure-redundancy and deterministic run-time adaptivity using real-time hardware reconfiguration and online-monitoring are important features for safety-critical embedded systems, e.g. for smart mobility in automotive, avionics, railway, etc. systems. Thus, scalability for corresponding E/E-Architectures, as we have experienced for the last 35 years is at its end as we enter new phases of technology constraints and certification conditions within such kind of cyber-physical mobility application domains. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), here multi-/many-Core solutions are actually the only alternative on the semiconductor roadmaps. This requires urgently new solutions for programming and integrating such kind of parallel and heterogenous architectures and platforms, e.g. especially not to block future innovations in these important application domains.

The keynote will finally discuss the corresponding challenges and specifically outline promising perspectives for future multi-/many-core as well as dynamically reconfigurable, complex, adaptive and reliable systems-on-chip, for embedded and especially automotive and avionics computing systems. This includes new industry-relevant approaches for necessary hardware/software/virtualization as well as tool integration solutions.

Magdy Bayoumi
University of Louisiana at Lafayette

"Smart Wireless Sensors Networks"


Magdy A. Bayoumi is the Z.L. Loflin Eminent Scholar Endowed Chair Professor at The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette (UL Lafayette). He was the Director of CACS, 1997 – 2013 and Department Head of the Computer Science Department, 2000-2011. Dr. Bayoumi has been a faculty member in CACS since 1985. He received B.Sc. and M.Sc. degrees in Electrical Engineering from Cairo University, Egypt; M.Sc. degree in Computer Engineering from Washington University, St. Louis; and Ph.D. degree in Electrical Engineering from the University of Windsor, Canada.

Dr. Bayoumi has graduated more than 60 Ph.D. and about 175 Master’s students. He has published over 500 papers in related journals and conferences. He edited, co-edited and co-authored 10 books in his research interests. He has been Guest Editor (or Co-Guest Editor) of ten Special Issues in VLSI Signal Processing, Learning on Silicon, Multimedia Architecture, Digital and Computational Video, and Perception-on-a-Chip, SoC, and Machine to Machine Interface. He has given numerous invited lectures and talks nationally and internationally, and has consulted in industry. He is an IEEE fellow.                                              

Dr. Bayoumi was the chair of an international delegation to China, sponsored by People-to-People Ambassador, 2000. He received the French Government Fellowship, University of Paris Orsay, 2003-2005 and 2009. He received the United Nation Fellowship, Egypt, 2002-2003. He was a Visiting Professor at King Saud University.

Dr. Bayoumi has served in many editorial, administrative, and leadership capacities in IEEE Signal Processing Society, IEEE Computer Society, and IEEE Circuits and Systems (CAS) Society, for the last 25 years. He has been involved in many conferences, serving in different capacities. He has been the general chair of more than ten conferences/workshops.

Michiko Inoue
Nara Institute of Science and Technology, Japan

“Challenges of LSI Test Technology toward Dependability through Life Cycle”

photo michikoMichiko Inoue received her B.E., M.E, and Ph.D degrees in computer science from Osaka University in 1987, 1989, and 1995 respectively. She worked at Fujitsu Laboratories Ltd. from 1989 to 1991. She is a Professor of Graduate School of Information Science, Nara institute of Science and Technology (NAIST). Her research interests include distributed algorithms, parallel algorithms, graph theory and design and test of digital systems. 
She is a member of Science Council of Japan, IEEE, the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and Japanese Society for Artificial Intelligence.

Abstract: LSI test technology has been investigated and developed mainly for manufacturing test of LSI products. Technology scaling and expansion to safety-critical applications require more accurate but cost efficient test, and these pose a many challenges to test technology. In addition, test technology is now expanding its usage to LSI dependability including reliability and security. This talk introduces current challenges of test technology for LSI dependability through its life cycle.

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