September 8-11, 2015
The Lakeview Hotel
Beijing, China

SOCC 2015 Tutorial Day Program

September 8, 2015

7:30AM – 10:00AM


8:30AM – 10:00AM

T1A (Da Xue Tang – 2)
Woogeun Rhee
Tsinghua Univ, China

Phase-Locked Clock Generation for SoC: Circuit and System Design Aspects

T1B (Da Xue Tang – 4)
Yu Huang and Janusz Rajski
Mentor Graphics, USA

SoC Testing

10:00AM – 10:30AM

Tea break

10:30AM – 12:00PM

T2A (Da Xue Tang – 2)
Ming-Dou Ker
NCTU, Taiwan

Advanced ESD Protection Design for CMOS Circuits and Systems

T2B (Da Xue Tang – 4)
Ramalingam Sridhar
SUNY at Buffalo, USA

Internet of Things (IoT) – Opportunities for SoC Designers

12:00PM – 1:30PM

Lunch break

1:30PM – 3:00PM

T3A (Da Xue Tang – 2)
Liming Xiu
Kairos Microsystems Corp.

From Frequency to Time-Average-Frequency: A paradigm Shift in the Design of Electronic Systems

T3B (Da Xue Tang – 4)
Mohammed Ismail
KUSTAR, Abu Dhabi, UAE

A Self-powered Biomedical SoC for Wearable Health Care

3:00PM – 3:30PM

Tea break

3:30PM – 5:00PM

T4A (Da Xue Tang – 2)
Gabriel Rincón-Mora
Georgia Inst. of Tech, USA

Tiny DC-Sourced Single Inductor Charge-Supply ICs

T4B (Da Xue Tang – 4)
Guangyu Sun
Peking University

Emerging Non-volatile Memory: Device, Circuit, and Architecture

T1A (Room: Da Xue Tang - 2)
Phase-Locked Clock Generation for SoC: System Perspectives for IC Designers

Woogeun Rhee, Institute of Microelectronics, Tsinghua Univ, Beijing

Abstract:A phase-locked loop is a key building block in wireline and wireless systems. In the wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data rate I/O links. In the wireless systems, the DS PLL based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics tailored for circuit designers. Then, system perspectives and practical circuit design aspects will be presented. Furthermore, various PLL architectures and design challenges will be discussed.

RheeBiography: Woogeun Rhee is a Professor at Tsinghua University, China. He received the B.S.E.E. degree from Seoul National University in 1991, the M.S.E.E. degree from UCLA, in 1993, and the Ph.D. degree from the University of Illinois, Urbana-Champaign, in 2001. From 1997 to 2001, he was with Conexant Systems, CA, where he was a Principal Engineer and developed low-power low-cost fractional-N synthesizers, e.g. CX74038. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, NY and worked on clocking area for high-speed I/O serial links. In August 2006, he joined the faculty of Tsinghua University, China. He currently holds 20 U.S. patents. He is a member of the TPC for IEEE ISSCC, CICC and A-SSCC conferences. He served as an Associate Editor of the IEEE TCAS-II (2007-2008) and is currently an Associate Editor of the IEEE Journal of Solid-State Circuits.

T2A (Room: Da Xue Tang - 2)
Advanced ESD Protection Design for CMOS Circuits and Systems
Ming-Dou Ker, National Chiao-Tung Univ., Taiwan

Abstract: To reduce the weight of electronic products, to integrate more functions into the electronic products, as well as to reduce the power consumption of electronic products, the CMOS technology has been developed into nanometer scale to realize VLSI/SoC for electronic systems. With the transistors in the nano-scale dimension, the gate-oxide thickness of MOSFET is only 10~15Å for operating with sub-1V power supply. Such thinner gate oxide is very easily ruptured by electrostatic discharge (ESD) events, which frequently happen in our environments with the voltage level of hundreds or even thousands volts. The integrated circuits (ICs) are weaker to sustain such ESD stresses during the assembly, testing, package, and the applications.

To verify the ESD reliability of IC products for safe applications, there are already some industry ESD test standards developed, such as Human Body Model (HBM) and Charged Device Model (CDM), to verify the ESD robustness of IC products. Besides, in the IEC 61000-4-2 standard, the electronic products are zapped by the ESD gun with ESD voltage of even up to 15kV in the air-discharge mode. How to design the on-chip ESD protection circuits to effectively protect the integrated circuits realized by the nano-scale CMOS devices is a quite difficult challenge to IC industry. The on-chip ESD protection circuit must be included in the beginning phase of chip design.

In this Tutorial, a brief introduction on ESD issue and test standards to IC products is presented with some failure analysis pictures from real IC products to demonstrate the impact of ESD on IC products. The basic design concept for on-chip ESD protection circuit will be presented. Some useful ESD protection designs for high-speed I/O and RF circuits will be mentioned. To achieve the whole-chip ESD protection by using the active power-rail ESD clamp circuit will be emphasized. Additional consideration on the active power-rail ESD clamp circuit realized in the nanoscale CMOS processes will be especially addressed. After the component-level ESD protection, the system-level ESD protection design will be brief discussed. ESD protection for CMOS ICs is not only the process issue but also highly dependent to the design issue, which has been an important topic that the IC designers need to know.

KerBiography: Ming-Dou Ker received the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1993. He ever worked in the Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. Now, he has been the Distinguished Professor in the Department of Electronics Engineering, National Chiao-Tung University, Taiwan; as well as the Chair Professor of I-Shou University, Kaohsiung, Taiwan. In the technical field of reliability and quality design for microelectronic circuits and systems, he has proposed many solutions to improve the reliability and quality of integrated circuits, which have been granted with hundreds of U.S. patents. He had been invited to teach and/or to consult the reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC industry. Prof. Ker has served as member of the Technical Program Committee and the Session Chair of numerous international conferences for many years. Prof. Ker was ever invited to give tutorial and/or invited talks in many international conferences (such as: ISCAS, CICC, IRPS, and ISSCC) and Universities. He ever served as the Associate Editor for the IEEE Transactions on VLSI Systems (2006-2007); the Distinguished Lecturer of IEEE Circuits and Systems Society (2006–2007); and the Distinguished Lecturer of IEEE Electron Devices Society (2008–2015). He was the Founding President of Taiwan ESD Association. Currently, he is the Editor of IEEE Transactions on Device and Materials Reliability. Since 2012, he has been the Dean of the College of Photonics, National Chiao-Tung University, Taiwan. Prof. Ker has been a Fellow of the IEEE since 2008.

T3A (Room: Da Xue Tang - 2)
From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic Systems

Liming Xiu, VP of Product Development, Kairos Microsystems Corporation

Abstract: Clock technology is one of the four fundamental technologies in the field of IC design. It is the timekeeper and the driver of everything inside a silicon chip. Time-Average-Frequency Direct Period Synthesis is an emerging technology in the field of on-chip frequency synthesis (clock generation). It comprises a new concept, a rigorous mathematical theory, and a novel circuit architecture. Its aim is the two long-lasting problems in this field: arbitrary frequency generation and instantaneous frequency switching. The goal is to achieve these two features on-a-chip simultaneously and at a reasonable cost so that SoC chip architects have a powerful clock generator in their hands to create their innovations at higher levels. It is a component-level enabler for chip-system-architecture level innovations. On a large scale, since clock is omnipresent in electronic system, this technology introduces a paradigm shift in electronic system design. In this tutorial, the Time-Average-Frequency concept will be explained. The circuit architecture will be briefly reviewed. Its impact, the route from component-level enabler to system level innovations, will be illustrated through real application examples. The newly published book in May 2015: “From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic System (IEEE Press Series on Microelectronic Systems)” will be provided to each tutorial attendant.

Liming XiuBiography: Liming Xiu earned his B.S. and M.S. degrees in physics from Tsinghua University, Beijing, China, in 1986 and 1988, respectively.  Mr. Xiu earned his second M.S. degree in electrical engineering from Texas A&M University, College Station, TX, USA, in 1995. In 1990-1993, he was a research scientist of University of Houston, TX, USA. In 1995-2009, he worked for Texas Instruments Inc., Dallas, TX, USA (Senior Member Technical Staff). In 2009-2012, he was chief clock architect of Novatek Microelectronics Corp., Hsinchu, Taiwan. Currently, he is involved in an IC design startup. He has 19 granted and 9 pending US patents and has published numerous IEEE journal papers and three books: VLSI Circuit Design Methodology Demystified (Wiley-IEEE Press), Nanometer Frequency Synthesis beyond Phase-Locked Loop (Wiley-IEEE Press, IEEE Press Series on Microelectronic Systems) and From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic system (Wiley-IEEE Press, IEEE Press Series on Microelectronic Systems). He is also an invited author of a chapter in an upcoming book “Mixed-Signal Circuits”. He is the inventor of Flying-Adder frequency synthesis architecture (Flying-Adder PLL); the promoter of Time-Average-Frequency concept and theory. He served as vice president of IEEE Circuit and Systems Society in years 2009-2010.

T4A (Room: Da Xue Tang - 2)
Tiny DC-Sourced Single-Inductor Charger-Supply ICs
Gabriel Rincón-Mora, Georgia Institute of Technology

Abstract: A challenge wireless micro-sensors and other microsystems face is short lifetime, because tiny batteries store little energy. Although miniaturized fuel cells and atomic sources store more energy than lithium ions and super capacitors, they source less power, so they cannot power as many functions. Unfortunately, their power-dense counterparts cannot sustain life for long. Thankfully, the environment also holds vast amounts of energy, and of typical sources, like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. The fact is, combining miniaturized fuel or photovoltaic cells with tiny lithium-ion batteries or super capacitors can be more compact, reliable, and longer lasting than any single technology. Managing a hybrid system of this sort to supply a microwatt application, however, requires an intelligent, low-loss dc-dc power converter. This talk discusses the state of the art in miniaturized charger–supply systems that draw power from an energy-dense dc source and supplementary power from a battery to supply a load and recharge the battery with excess power from the energy-dense source.

Rincon-MoraBiography: Prof. Gabriel A. Rincón-Mora (B.S., M.S., Ph.D.) worked for Texas Instruments in 1994-2003, was an Adjunct Professor at Georgia Tech in 1999-2001, and has been a Professor at Georgia Tech since 2001 and a Visiting Professor at National Cheng Kung University in Taiwan since 2011. He is a Fellow of the IEEE and the IET, and his scholarly products include 9 books, 4 book chapters, 38 patents issued, over 160 article publications, over 26 commercial power-chip designs, and over 95 invited talks. Awards include the National Hispanic in Technology Award from the Society of Professional Hispanic Engineers, the Charles E. Perry Visionary Award from Florida International University, a Commendation Certificate from the Lieutenant Governor of California, the IEEE Service Award from IEEE CASS, the Orgullo Hispano and the Hispanic Heritage awards from Robins Air Force Base, and two "Thank a Teacher" certificates from Georgia Tech. Georgia Tech inducted him into the Council of Outstanding Young Engineering Alumni in 2000 and Hispanic Business magazine named him one of "The 100 Most Influential Hispanics" in 2000. He has served as Distinguished Lecturer, General Chair, Technical Program Chair and Co-Chair, Associate Editor, Guest Editor and Co-Editor, and Chapter Chair and Vice-Chair on multiple occasions for IEEE, several international conferences, and several journal publications.

T1B(Room: Da Xue Tang - 4)
SoC Testing
Yu Huang and Janusz Rajski, Mentor Graphics Co, USA

Abstract : This tutorial covers fundamental concepts, recent developments and industry practices
on SoC hierarchical and modular test flow. It has two sections:

  1. Core-level test technologies: In this section, we will cover three important topics in core-level DFT and ATPG.
    1. Test quality. We will introduce cell-aware ATPG. Industrial case studies will be used to illustrate this new fault model’s contributions to test quality.
    2. Test compressions. We will first review the basics of the test compression technologies, which include test stimuli compression and test responses compaction. In the test stimuli compression, we will focus on continuous-flowbased technology, such as Embedded Deterministic Test (EDT). For the test responses compaction, we will briefly introduce space compaction, time compaction and hybrid compaction. Low power compression technologies will also be reviewed.
    3. Test point insertion. In the good old days, test point was used to improve the test coverage. However, the new trend in test industry is to use the new test point insertion technologies to reduce the pattern count.
  2. SoC-level test technologies: In this section, we will cover the following important topics in SoC-level Testing
    1. This section starts with a review on published core-based SoC hierarchical DFT methodologies and techniques such as TAM, wrapper, test scheduling, and diagnosis etc.
    2. Illustrate SoC modular test flow and technologies such as broadcasting compressed test stimuli to multiple identical and non-identical cores, channel scaling, and flexible test accessible channels to optimize SoC pin utilization and reduce total SoC test time.
    3. Pattern retargeting based hierarchical SoC test and diagnosis flow. Dynamic bandwidth management will be explained. It can take advantage of pattern retargeting flow and achieve higher SoC test time reduction. IEEE 1687 (IJTAG) applications in the SoC test flow. This new IEEE standard makes cores to be tested at SoC in a plug-and-play manner.

HuangBiography: Yu Huang is a Principal Engineer in the Silicon Test Systems Division of Mentor Graphics. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He has a BS in electronic science and an MS in semiconductor devices and technology, both from Nankai University, China; and a PhD in electrical and computer engineering from the University of Iowa. He holds 7 US patents and has 18 patents pending. He has published more than 100 papers on leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, ATS, ETS, ASPDAC, NATW and some other conferences and workshops in the testing area.

Biography: Janusz Rajski is a chief scientist and the director of engineering for the Silicon Test Solutions products group at Mentor Graphics. He manages an R&D organization with centers in US, Canada, Germany, India and Poland. He has published more than 200 research papers in these areas and is co-inventor of 80 US and 27 international patents. He is a co-author of Arithmetic Built-In Self-Test for Embedded Systems (Englewood Cliffs, NJ: Prentice-Hall, 1997). He is also the principal inventor of Embedded Deterministic Test (EDT™) technology used in the first commercial test compression product TestKompress. He was the co-recipient of the 1993 Best Paper Award for the paper on logic synthesis published in the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, co-recipient of the 1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, co-recipient of the 1999 and 2003 Honorable Mention Awards at the IEEE International Test Conference, co-recipient of the 2008 Best Paper Award at the Asian Test Symposium, and 2009 Best Paper Award at the VLSI Design, co-recipient of the 2010 Best Paper Award at the IEEE European Test Symposium, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the paper on Embedded Deterministic Test published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He served as Program Chair of the IEEE International Test Conference. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor's DFT business to its current position as #1 test business in EDA”. In 2011 Janusz
was elevated to the grade of IEEE Fellow for” contributions to VLSI circuit testing and test compression”.

T2B (Room: Da Xue Tang - 4)
Internet of Things (IoT) - Opportunities for SoC Designers
Ramalingam Sridhar, SUNY at Buffalo

Abstract: Internet of Things (IoT) is considered to be a technological trend that is likely to have a far reaching impact on every one's lives in many distinct ways. IoTs changs the internet from internet for people to internet of things. Enabling of IoT is accomplished through efforts by hardware and network industry and the enormous amount of data generated through IoTs impacts Big Data and data mining fields.

With its wide ranging applications in Healthcare, Home automation, Industrial Control and environmental and social domains, IoTs can have wide ranging expectations. Major roadblocks to the deployment and prevalent use of IoTs are power and privacy-security vulnerabilities. IoTs have conflicting requirements and choosing appropriate tradeoffs based on the situation will lead to its increased use. Though varying projections have large investment in IoTs, there is also increased skepticism due to privacy and security concerns. This tutorial will introduce IoTs, specifications, opportunities for SoC designers and their integration into diverse applications. Possible solutions will be discussed in dealing with power and security aspects as well.

sridhar smallBiography: Prof Ram Sridhar is the Director of High Performance VLSI Systems and Architecture Lab at University at Buffalo, Computer Science and Engineering Department. He has a Ph.D. from Washington State University and has published numerous articles in VLSI systems, power aware systems, computer architecture, wireless networks and security. He is also active as a volunteer with leading conferences in these areas in many capacities, including as the Conference Chair. Prof Sridhar is a senior member of IEEE and was IEEE CAS Distinguished Lecturer.

T3B (Room: Da Xue Tang - 4)
A Self-powered Biomedical SoC for Wearable Health Care
Mohammed Ismail, KUSTAR, Abu Dhabi, UAE

Abstract: This talk will focus on Systems-on-Chip (SoCs) presented as part of the UAE SRC (Semiconductor Research Corp) Center of Excellence on Energy Efficient Electronic Systems (aka ACE4S ) involving researchers from 5 UAE Universities looking at developing new technologies aiming at innovative self-powered wireless sensing and monitoring SoC platforms. The research targets applications in self-powered chip sets for use in public health, ambient intelligence, safety and security and water quality. ACE4S is the first SRC center of excellence outside the US.

One such application, which we will discuss in details, is a novel SoC platform for wearable health care. More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system. The system achieved an accuracy of 99%. The ECG signal is sensed using a flexible, dry, MEMS-based technology and the system is powered up by harvesting human thermal energy. The system architecture is implemented in Global foundries' 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating frequency of 10 KHz and from a supply voltage of 1.2V. To our knowledge, this is the first SoC implementation of an ECG-based processor that is capable of predicting ventricular arrhythmia hours before the onset and with an accuracy of 99%.

IsmailBiographyDr. Ismail, a prolific author and entrepreneur in the field of chip design and test, spent over 20 years in academia and industry in the US and Europe and is the Founder of the Ohio State University's (OSU) Analog VLSI Lab , one of the foremost research entities in the field of analog, mixed signal and RF integrated circuits. He also served on the Faculty of OSU's ElectroScience Lab. He held a Research Chair at the Swedish Royal Institute of Technology (KTH) where he founded the RaMSiS (Radio and Mixed Signal Integrated Systems) Research Group there. He had visiting appointments in Finland (Aalto university), Norway (NTH and University of Oslo), the Netherlands (Twente University) and Japan (Tokyo Institute of Technology).

He Joined KUSTAR, the UAE in 2011, where he holds the ATIC Professor Chair and is Head of the ECE Department which exists on both KUSTAR's campuses in Sharjah and Abu Dhabi. He is also serving as Director of the Khalifa Semiconductor Research Center (KSRC) and Co-Director of the ATIC-SRC Center of Excellence on Energy Efficient Electronic systems (ACE4S) targeting self-powered chip sets for wireless sensing and monitoring, bio chips and power management solutions. His current research focuses on "self- healing" design techniques for CMOS RF and mm-wave ICs in deep nanometer nodes.

Dr.Ismail served as a Corporate Consultant to over 30 companies and is a Co-Founder of Micrys Inc., Columbus, Ohio, Spirea AB, Stockholm, Firstpass Technologies Inc., Dublin, Ohio and ANACAD-Egypt (now part of Mentor Graphics). He advised the work of over 50 Ph.D. students and of over 100 M.S. students. He authored or co-authored over 20 books and over 150 journal publications and has 8 US patents issued and several pending. He is the Founding Editor of the Springer Journal of Analog Integrated Circuits and Signal Processing and serves as the Journal's Editor-in-Chief. He served the IEEE in many editorial and administrative capacities. He is the Founder of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), the flagship Region 8 Conference of the IEEE Circuits and Systems Society. He received the US Presidential Young Investigator Award, the Ohio State Lumley Research Award four times, in 1992, 1997, 2002 and 2007 and the US Semiconductor Research Corporation's Inventor Recognition Award twice. He is a Fellow of IEEE.

T4B (Room: Da Xue Tang - 4)
Emerging Non-volatile Memory: Device, Circuit, and Architecture

Guangyu Sun
Peking University


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